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Updated: May 10, 2025

Planar and Three-Dimensional Printing of Conductive Inks
Published on: December 9, 2011
Miniaturized Micrometer-Level Copper Wiring and Electrodes Based on Reverse-Offset Printing for Flexible Circuits
Kim Eiroma1, Asko Sneck1, Olli Halonen1
1VTT Technical Research Centre of Finland, Ltd., Tietotie 3, FI-02150 Espoo, Finland.
Abstract:
High-resolution reverse-offset printing (ROP) is developed for miniaturization of printed electronics, resulting in a notable decrease in material usage compared to conventional printing processes. Two alternative ROP processes for patterning of metal conductors are available that are comparable in their cost per sample: direct nanoparticle (NP) printing (e.g., Ag and Cu) and patterning of vacuum-deposited metal (Ag, Al, Au, Cu, Ti, etc.) films using ROP printed polymer resist ink and the lift-off (LO) process. In this work, we focus on ROP of Cu NP ink followed by intense pulsed light (IPL) sintering and vacuum-deposited Cu patterned by ROP lift-off (LO). The good large-scale uniformity of the two processes is demonstrated by a grid of 300 individual thickness, sheet resistance, and resistivity measurement points with low variation over the 10 cm × 10 cm printed sample area. Sheet resistances of 0.56 ± 0.03 and 1.23 ± 0.05 Ω/□ are obtained at 113 and 40 nm thickness for Cu NP and Cu LO, respectively. Both processes show <5% thickness variation over a large area. A line-space (L/S) resolution of 2 μm is obtained for ROP patterned vacuum-deposited Cu having very low line edge roughness (LER) (∼60 nm), whereas for direct ROP printed Cu NP ink, the L/S resolution (2-4 μm) is limited by LER (∼900 nm) and influenced by the printed layer thickness. Based on the two fabrication routes, a flexible chip component assembly process is presented. Preliminary bending resistance results indicate that both ROP-based patterning processes yield a robust electrical interconnection between the ultrathin polyimide (PI) 5 mm × 5 mm chip and thermoplastic polyurethane (TPU). ROP shows promise as a scalable and sustainable patterning method for flexible ICs/chips that are assembled on flexible, stretchable, or biodegradable substrates and used, e.g., in wearable, large-scale sensing, and in environmental monitoring.
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