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Updated: Sep 16, 2025

A Standard and Reliable Method to Fabricate Two-Dimensional Nanoelectronics
Published on: August 28, 2018
Wafer-Scale High Mobility 2D Tellurium Thin-Film Transistor for Heterogeneous Integrated 3D-CFET Logic Circuits
Yalun Tang1, Yilong Song1, Longhui Zeng1
1Department of Electrical and Computer Engineering, University of California San Diego, 9500 Gilman Dr., La Jolla, California, 92093, United States.
Abstract:
Back-end-of-line (BEOL)-compatible complementary field-effect transistor (CFET), which vertically integrates p-channel and n-channel thin-film transistors (TFT) in a 3D architecture on Si-CMOS, is critical for next-generation electronics, enabling higher functionality and improved energy efficiency. However, the absence of a high-performance BEOL-compatible p-channel TFT, the counterpart of n-channel oxide-TFT, continues to pose a significant challenge for the development of wafer-scale CFET technology. Tellurium (Te) has recently emerged as a promising candidate for p-channel TFT, but its device performance is not yet satisfactory. Here, in-plane crystal-oriented 2D Te channel thin-film is successfully grown to improve its carrier transport and successfully demonstrated high mobility p-channel Te-TFT with high saturation mobility (≈31 cm2 V s-1). The maximum process temperature is as low as 150 °C, enabling the fabrication of 3D-vertical CFET device with heterogeneous integration with oxide-TFTs on a 2-inch wafer. The hybrid CFET, composed of 2D p-Te and n-a-IGZO TFTs, exhibits an excellent inverter characteristic with a high voltage gain of 162 at VDD = 4 V. This study highlights the potential of low-temperature processed p-channel Te-TFTs for BEOL heterogeneous-compatible integration with oxide-TFT technology, providing enhanced functionality and high energy-efficiency for next-generation electronics.
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