Energy-efficient design of CNTFET-based quaternary arithmetic circuits

The vast interconnection between digital logic blocks is the main challenge faced in chip designing, which leads to increased area overheads and average power consumption. One possible solution to overcome this challenge is to make use of multi-valued logic. However, for implementing multi-valued logic, new design techniques that deliver low-power and high-speed performance need to be explored. In this paper, carbon nanotube field effect transistor (CNTFET) based standard quaternary logic gates have been designed using pass transistor logic and voltage divider circuit techniques. The simulation results for the standard quaternary logic gates have been obtained using HSPICE with standard 32 nm CNTFET Stanford model. The results for the standard quaternary inverter circuit at a supply voltage of 0.9 V show average power consumption, delay, power delay product (PDP), energy delay product (EDP), and area of 31.446 nW, 7.948 ps, 0.249 aJ, 1.986 × 10^-30 Js, and 13,287 λ², respectively. Similarly, the performance metrics, i.e., PDP and EDP are 0.597 aJ and 6.535 × 10^-30 Js for standard quaternary NAND circuit and 0.099 aJ and 1.046 × 10^-30 Js for standard quaternary NOR circuit, respectively. The proposed designs are superior in power consumption, PDP, and EDP in contrast to existing designs. The area occupancy and robustness of proposed standard quaternary inverter is also investigated by implementing layouts and performing Monte Carlo simulations. Further, the functionality of proposed quaternary logic gates is verified by using quaternary multiplier (QMUL) and quaternary half adder (QHA) as application examples. The proposed QMUL and QHA show PDP of 97.60 aJ and 95.937 aJ, respectively, which are quite encouraging when compared with literature. The new methodology for designing quaternary circuits reported in this work is expected to improve the performance of computing devices.