Energy-efficient design of CNTFET-based quaternary arithmetic circuits.

Area of Science:

• Electrical Engineering
• Computer Engineering
• Materials Science

Background:

• Interconnectivity in chip design increases area and power consumption.
• Multi-valued logic offers a potential solution to these challenges.
• New design techniques are needed for efficient multi-valued logic implementation.

Purpose of the Study:

• To design and evaluate carbon nanotube field effect transistor (CNTFET) based standard quaternary logic gates.
• To explore pass transistor logic and voltage divider circuit techniques for low-power, high-speed performance.
• To demonstrate the superiority of proposed designs over existing ones in terms of power consumption, PDP, and EDP.

Main Methods:

• Designed standard quaternary logic gates using CNTFETs.
• Employed pass transistor logic and voltage divider circuit techniques.
• Simulated designs using HSPICE with a 32 nm CNTFET Stanford model.
• Investigated area occupancy and robustness via layout and Monte Carlo simulations.

Main Results:

• Achieved low average power consumption (e.g., 31.446 nW for inverter) and delay (e.g., 7.948 ps for inverter).
• Demonstrated superior Power Delay Product (PDP) and Energy Delay Product (EDP) compared to existing designs.
• Verified functionality using quaternary multiplier (QMUL) and quaternary half adder (QHA) applications with competitive PDP values.

Conclusions:

• Proposed CNTFET-based quaternary logic gates offer significant improvements in power efficiency and speed.
• The new design methodology is expected to enhance the performance of computing devices.
• The designs show robustness and reduced area overhead, making them suitable for advanced integrated circuits.