On-Wafer Gate Screening Test for Improved Pre-Reliability in p-GaN HEMTs.

Area of Science:

• Materials Science
• Semiconductor Device Physics
• Reliability Engineering

Background:

• Gate robustness in p-GaN HEMTs is critical for device lifetime and meeting industry standards.
• Current reliability testing is time-consuming and typically performed post-packaging.
• A need exists for faster, on-wafer screening methods to identify potential gate failures early.

Purpose of the Study:

• To develop and validate a rapid, room-temperature screening procedure for p-GaN HEMT gate reliability.
• To evaluate the effectiveness of a dielectric layer and a surface treatment on gate pre-reliability.
• To understand the underlying mechanisms of gate leakage and drain leakage through simulations.

Main Methods:

• Development of a room-temperature stress procedure for on-wafer gate reliability testing.
• Comparative analysis of devices with a reference gate process, a dielectric layer process, and a surface treatment process.
• Utilizing Technology Computer-Aided Design (TCAD) simulations to investigate device behavior.

Main Results:

• The reference gate process exhibited significant gate leakage degradation under stress.
• Implementing a dielectric layer improved gate reliability but led to high drain leakage.
• A p-GaN surface treatment enhanced gate pre-reliability while maintaining low drain leakage.

Conclusions:

• The developed room-temperature screening method effectively identifies gate reliability issues early in the fabrication process.
• Surface treatment offers a promising approach to enhance p-GaN HEMT gate robustness without compromising drain leakage performance.
• TCAD simulations are valuable for understanding device physics and optimizing fabrication processes.