Power optimized quaternary logic circuits based on CNTFETs

Carbon nanotube field effect transistor (CNTFET) based multivalued logic (MVL) circuits capable of delivering high computational efficiency are required in contemporary digital systems for resolving data transfer issues. Quaternary logic can lead to the reduction of interconnections, as more information can be transferred by using four logic levels in high-speed and high-density. This work proposes novel standard quaternary inverter, SQNAND and SQNOR logic gates based on the stacking technique. These novel gates have been used in the design of a quaternary half adder. The simulation results for proposed quaternary circuits have been obtained using HSPICE with the 32 nm CNTFET Stanford model. The proposed designs of SQI, SQNAND, and SQNOR circuits are operated at a supply voltage of 0.9 V and show power delay product (PDP) of 0.776, 1.523, and 2.746 aJ, respectively. The area consumed by SQI, SQNAND, and SQNOR circuits is 7636, 16,456, 16,864 λ², respectively. Further, the power consumption and PDP for the proposed QHA are 1.01 µW and 0.806 10^-16 J, respectively. The proposed QHA shows improvement in PDP in contrast to other QHA designs reported earlier and is anticipated to be used for futuristic computing systems.