Extremely Uniform Growth Integration of Stacked Silicon Nanowire Channels for High-Performance Transistors via an...

Bottom-up catalytic growth has proven to be an exceptionally powerful method for producing ultrathin silicon nanowires (SiNWs) through a low-temperature, high-yield process. However, in order to serve as quasi-one-dimensional (1D) channels for building high-performance field effect transistors (FETs) within monolithic three-dimensional (3D) integration architectures, the diameter uniformity and spatial arrangement of these catalytical SiNWs have to be precisely controlled. In this work, we report on an embedded-precursor-feeding (EPF) strategy to accomplish an extremely uniform growth integration of horizontally stacked SiNWs arrays, with a diameter of D_nw = 20 ± 2 nm and a high growth yield >90%. Specifically, these SiNWs were produced via the indium droplet-catalyzed in-plane solid-liquid-solid (IPSLS) mechanism, where the amorphous silicon (a-Si) precursor layer has been embedded within the vertical SiN_x/SiO₂ sidewall grooves through a simple anisotropic etching. It has been found that the removal of the exposed a-Si precursor on the protrusive sidewalls and the exposed areas can completely suppress the undesired growth derailing or track-striding among neighbor SiNWs, as well as the random growth on the top and bottom platforms. Based on these rather uniform SiNW channels, prototype fin-gate FETs were successfully fabricated, achieving a high on/off current ratio of ∼10⁸ and a subthreshold swing of ∼160 mV/dec. This convenient but rather effective EPF strategy represents a key capability to establish the catalytical IPSLS growth as a reliable growth-in-place integration approach to batch-manufacture advantageous SiNW channels for building high-performance FETs in monolithic 3D integration architecture.