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Updated: Jan 11, 2026

A Standard and Reliable Method to Fabricate Two-Dimensional Nanoelectronics
Published on: August 28, 2018
Physics-based compact model for 2D TMD FETs with full-range validation from single device to circuit
Dokyoung Lee1,2, Jeongyun Jang1, Jimin Han1
1Division of Electronic and Semiconductor Engineering, Ewha Womans University, Seoul 03670, Republic of Korea. sunghok@ewha.ac.kr.
Abstract:
Two-dimensional (2D) semiconductors, particularly transition-metal dichalcogenides (TMDs), offer transformative potential for next-generation electronics because of their ultrathin atomic structures and superior electrostatic gate control. However, the practical realization of complex integrated circuits based on 2D TMD-based field-effect transistors (2D FETs) is critically constrained by the absence of robust, accurate, compact, and computationally efficient models suitable for SPICE (simulation program with integrated circuit emphasis)-based circuit simulations. This study demonstrated a physics-based, fully analytical, and SPICE-compatible compact model for 2D FETs. The model introduces a continuous, closed-form analytical framework that incorporates key physical mechanisms, such as interface trap states and gate-bias-dependent mobility degradation, through an efficient approximation of the Lambert W function. By avoiding iterative solvers and artificial segmentation, the model ensures compatibility with circuit simulators while maintaining high fidelity. Extensive validation against experimental data demonstrated quantitative agreement between the model and either single-device characteristics or the dynamic behavior of various circuits, including inverters, SRAM cells, NAND gates, and ring oscillators. Overall, the study established a robust and scalable modeling approach that effectively bridges device-level physics and system-level circuit designs for 2D semiconductors.
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