Programming pulse width dependent charge retention characteristics of low-power synaptic thin film transistors

A study on a programming-pulse width dependent synaptic characteristics of a sub-threshold operating hafnium doped zinc oxide (Hf-ZnO) thin-film transistor (TFT) is presented. For this, the static and pulsed characteristics of fabricated Hf-ZnO TFTs need to be monitored, respectively. Here, to achieve the memory capability (e.g. electron trapping and de-trapping) of this Hf-ZnO TFT, trap states in defective gate oxides, such as Al₂O₃ and HfO_x, caused by its low-temperature process with a thermal atomic-layer deposition can intentionally be used. Based on this memory phenomenon, when positive or negative programming-pulses are applied to the gate terminal, as decreasing the pulse width, it is observed that the programming speed is slower. However, in terms of the retention performance, a much longer retention time is confirmed from the mathematical modeling analysis with the stretched exponential function. In this vein, a trade-off relation between the programming speed and retention time is proposed. Besides these characteristics, such as the weight-update and retention characteristics, a paired-pulse depression and facilitation, and weight linearity are monitored to discuss the synaptic functionalities of Hf-ZnO TFTs further. Moreover, with this data at the device level, the crossbar simulation based on the analog accelerator is conducted, monitoring its performance (i.e. a classification accuracy).