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Updated: Jan 10, 2026

A Fabrication and Measurement Method for a Flexible Ferroelectric Element Based on Van Der Waals Heteroepitaxy
Published on: April 8, 2018
Ferroelectric transistors for low-power NAND flash memory
Sijung Yoo1, Taek Jung Kim1, Seung-Geol Nam1
1Thin Film Technical Unit, Device Research Center, Samsung Advanced Institute of Technology (SAIT), Samsung Electronics, Suwon, Korea.
Abstract:
NAND flash memory is essential in modern storage technology, amid growing demands for low-power operation fuelled by data-centric computing and artificial intelligence1,2. Its unique 'string' architecture3, where multiple cells are connected in series, requires high-voltage pass operation that causes a large amount of undesired power consumption4. Lowering the pass voltage, however, poses a challenge: it leads to an associated reduction in the memory window, restricting the multi-level operation capability. Here, with a gate stack composed of zirconium-doped hafnia and an oxide semiconductor channel, we report ultralow-power ferroelectric field-effect transistors (FeFETs) that resolve this dilemma. Our FeFETs secure up to 5-bit per cell multi-level capability, which is on par with or even exceeds current NAND technology, while showing nearly zero pass voltage, saving up to 96% power in string-level operations over conventional counterparts. Three-dimensional integration of FeFET stacks into vertical structures with a 25-nm short channel preserves robust electrical properties and highlights low-pass-voltage string operation in scaled dimensions. Our work paves the way for next-generation storage memory with enhanced capacity, power efficiency and reliability.
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