Gate Metal Defect Screening at Wafer-Level for Improvement of HTGB in Power GaN HEMT

The increasing market demand for high-power and high-frequency applications necessitates the development of highly reliable Gallium Nitride (GaN) High-Electron-Mobility Transistors (HEMTs). While GaN offers superior performance and efficiency over traditional silicon, gate-related defects pose a significant reliability challenge, often leading to premature device failure under stress. Traditional High-Temperature Gate Bias (HTGB) testing is effective but time-consuming and costly, particularly when defects are only identified post-packaging. This study focuses on developing an effective wafer-level screening methodology to mitigate the financial burden and reputational risk associated with late-stage defect discovery. Failure analysis of an HTGB premature failure revealed a gate metal deposition defect characterized by identical elemental composition to the bulk metal, suggesting a small-volume structural anomaly. Crucially, a comparative analysis showed that Forward Gate Current (I_GON) is an insensitive screening metric due to high inherent gate leakage through the passivation layer. In contrast, the Reverse Gate Current (I_GOFF) exhibited sensitivity, particularly under the tensile stress induced by package molding, which is attributed to the piezoelectric effect altering the depletion region width beneath the p-GaN gate. Based on this observation, a multi-pulse I_DSS test was developed as a wafer-level screen. This method successfully amplified the subtle electrical field perturbations caused by the gate defect. After screening 231 dies using the new methodology, zero failures were recorded after 1000 h of HTGB stress, a significant improvement over the initial failure rate of 0.43% (1 out of 231). This work demonstrates that early, sensitive wafer-level screening of gate defects is indispensable for optimizing manufacturing yield and enhancing long-term device reliability.