Endurance Paradox in Hafnium-Oxide-Based Silicon-Channel Ferroelectric Transistors

Area of Science:

• Materials Science
• Electrical Engineering
• Semiconductor Physics

Background:

• Hafnium-oxide ferroelectric transistors show promise for nonvolatile memory.
• Limited endurance (approx. 10^4 cycles) hinders practical application.

Purpose of the Study:

• Investigate the root cause of premature endurance failure in these devices.
• Determine if failure originates from the ferroelectric layer or other components.

Main Methods:

• Electrical characterization of degraded ferroelectric gate stacks.
• Analysis of polarization switching post-memory-window closure.
• Interface charge trapping and screening analysis.

Main Results:

• Ferroelectric polarization switching remains intact even after device failure.
• Transistor-level memory operation collapses due to interface degradation.
• Charge trapping at the interface reduces threshold-voltage contrast.

Conclusions:

• Endurance failure is primarily caused by interface degradation, not ferroelectric fatigue.
• The ferroelectric layer itself remains functional, indicating potential for improved device design.
• Addressing interface issues is crucial for enhancing ferroelectric transistor endurance.