A Subsampling Phase-Locked Loop with a Dual Charge Pump Based on Capacitor Multipliers for CMOS Image Sensor.

Area of Science:

• Integrated Circuits
• Signal Processing

Background:

• Traditional sub-sampling phase-locked loops (SSPLLs) face challenges with stability, spur degradation, and area overhead.
• Existing zero-compensation techniques often worsen performance or increase chip size, limiting their use in high-resolution image sensors.

Purpose of the Study:

• To propose a novel SSPLL design that overcomes the limitations of traditional methods.
• To enhance SSPLL performance in terms of stability, jitter, spurs, power consumption, and area.

Main Methods:

• Introduced a capacitor multiplication technique utilizing dual charge pumps (CP1 and CP2) with inversely synchronized charge/discharge states.
• Implemented a coordinated operational scheme to amplify loop filter capacitance without increasing physical layout area.
• Integrated zero-compensation technology to maintain SSPLL stability.

Main Results:

• The proposed SSPLL, designed in a 55 nm CMOS process, achieved a spot phase noise of -131.5 dBc/Hz at 1 MHz offset (1.2 GHz output frequency).
• Demonstrated integrated RMS jitter of 549 fs (10 kHz–40 MHz spectrum) and spurs suppressed to -51.3 dB.
• Achieved power efficiency of 3.81 mW and a compact layout area of 0.064 mm².

Conclusions:

• The novel dual-charge pump (CP) charge multiplication technology effectively reduces jitter and power consumption while minimizing layout area.
• This SSPLL design offers a viable technical solution for high-resolution image sensor applications.