High-density three-dimensional integration of dynamic random-access memory using vertical dual-gate IGZO TFTs.

Area of Science:

• Materials Science
• Electrical Engineering
• Computer Science

Background:

• Artificial intelligence (AI) deployment faces memory density bottlenecks.
• Current three-dimensional (3D) dynamic random-access memory (DRAM) integration challenges include misalignment and thermal cycling.
• Novel memory cell architectures are needed to enhance AI performance.

Purpose of the Study:

• To present a 3D DRAM architecture enabling higher memory density for AI.
• To address challenges in 3D DRAM integration, specifically lateral misalignment and thermal cycling.
• To demonstrate a scalable and reliable memory solution for near-memory computing.

Main Methods:

• Developed a vertical dual-gate two-transistors-zero-capacitor memory cell architecture.
• Employed a single-step process for simultaneous stacking of dual-gate In-Ga-Zn-O transistors.
• Optimized contact metallization and interface using in-situ ozone oxidation.
• Demonstrated four-bit multi-bit operation in an ultra-scaled 4F² 2T0C DRAM.

Main Results:

• Achieved higher memory density through a novel 3D DRAM architecture.
• Overcame misalignment and thermal cycling issues using a single-step stacking process.
• Vertical dual-gate transistors exhibited high on-state current, small subthreshold slope, and improved thermal stability.
• Demonstrated reliable four-bit multi-bit operation in ultra-scaled DRAM cells.

Conclusions:

• The presented 3D DRAM architecture offers a promising solution to AI memory bottlenecks.
• The single-step stacking process and optimized transistors enhance scalability and reliability.
• This approach facilitates more efficient near-memory computing for advanced AI systems.