Jove
Visualize
Contact Us
JoVE
x logofacebook logolinkedin logoyoutube logo
ABOUT JoVE
OverviewLeadershipBlogJoVE Help Center
AUTHORS
Publishing ProcessEditorial BoardScope & PoliciesPeer ReviewFAQSubmit
LIBRARIANS
TestimonialsSubscriptionsAccessResourcesLibrary Advisory BoardFAQ
RESEARCH
JoVE JournalMethods CollectionsJoVE Encyclopedia of ExperimentsArchive
EDUCATION
JoVE CoreJoVE BusinessJoVE Science EducationJoVE Lab ManualFaculty Resource CenterFaculty Site
Terms & Conditions of Use
Privacy Policy
Policies

Related Concept Videos

Biasing of Metal-Semiconductor Junctions01:27

Biasing of Metal-Semiconductor Junctions

747
Biasing metal-semiconductor junctions involves applying a voltage across the junction. Specifically, the metal is connected to a voltage source, while the semiconductor is grounded. This technique is essential for controlling the direction and magnitude of current flow in electronic devices, including diodes, transistors, and photovoltaic cells.
In Schottky junctions, where the semiconductor is n-type, applying a positive voltage to the metal relative to the semiconductor reduces its Fermi...
747

You might also read

Related Articles

Articles linked to this work by shared authors, journal, and citation graph.

Sort by
Same author

Uniform TiN-Capped Co Buried Bit Lines for 4F<sup>2</sup> DRAM Vertical Channel Transistors: Mitigating Agglomeration with Co Nitridation.

ACS omega·2026
Same author

High-density three-dimensional integration of dynamic random-access memory using vertical dual-gate IGZO TFTs.

Nature communications·2025
Same author

High-fidelity geometric quantum gates exceeding 99.9% in germanium quantum dots.

Nature communications·2025
Same author

Low Temperature (Down to 6 K) and Quantum Transport Characteristics of Stacked Nanosheet Transistors with a High-K/Metal Gate-Last Process.

Nanomaterials (Basel, Switzerland)·2024
Same author

CMOS Scaling for the 5 nm Node and Beyond: Device, Process and Technology.

Nanomaterials (Basel, Switzerland)·2024
Same author

Amorphous oxide semiconductor for monolithic 3D DRAM: an enabler or passer-by?

National science review·2024

Related Experiment Video

Updated: Mar 14, 2026

Fabrication of a Solution-gated Indium-Tin-Oxide-based One-piece Transistor Enabling Sensitive Biosensing
10:45

Fabrication of a Solution-gated Indium-Tin-Oxide-based One-piece Transistor Enabling Sensitive Biosensing

Published on: August 29, 2025

808

In Situ Engineering of Vertical Indium Gradients via Sputtering Kinetics for High-Performance IGZO Channel-All-Around

Jiabao Sun1, Wei Yu1, Jing Zhang1

  • 1Beijing Superstring Academy of Memory Technology, Beijing 100176, China.

Nano Letters
|March 13, 2026
PubMed
Summary

This study introduces a novel indium-gradient channel for vertical channel-all-around (VCAA) transistors, significantly boosting performance. The engineered channel reduces contact resistance and enhances drive-current for advanced 3D integrated circuits.

Keywords:
contact resistance asymmetrygradient channelindium−gallium−zinc oxide (IGZO)monolithic 3D integrationsputtering kineticsvertical channel-all-around (VCAA) FETs

More Related Videos

Fabrication of Schottky Diodes on Zn-polar BeMgZnO/ZnO Heterostructure Grown by Plasma-assisted Molecular Beam Epitaxy
14:16

Fabrication of Schottky Diodes on Zn-polar BeMgZnO/ZnO Heterostructure Grown by Plasma-assisted Molecular Beam Epitaxy

Published on: October 23, 2018

8.2K
In Situ Transmission Electron Microscopy with Biasing and Fabrication of Asymmetric Crossbars Based on Mixed-Phased a-VOx
09:49

In Situ Transmission Electron Microscopy with Biasing and Fabrication of Asymmetric Crossbars Based on Mixed-Phased a-VOx

Published on: May 13, 2020

4.4K

Related Experiment Videos

Last Updated: Mar 14, 2026

Fabrication of a Solution-gated Indium-Tin-Oxide-based One-piece Transistor Enabling Sensitive Biosensing
10:45

Fabrication of a Solution-gated Indium-Tin-Oxide-based One-piece Transistor Enabling Sensitive Biosensing

Published on: August 29, 2025

808
Fabrication of Schottky Diodes on Zn-polar BeMgZnO/ZnO Heterostructure Grown by Plasma-assisted Molecular Beam Epitaxy
14:16

Fabrication of Schottky Diodes on Zn-polar BeMgZnO/ZnO Heterostructure Grown by Plasma-assisted Molecular Beam Epitaxy

Published on: October 23, 2018

8.2K
In Situ Transmission Electron Microscopy with Biasing and Fabrication of Asymmetric Crossbars Based on Mixed-Phased a-VOx
09:49

In Situ Transmission Electron Microscopy with Biasing and Fabrication of Asymmetric Crossbars Based on Mixed-Phased a-VOx

Published on: May 13, 2020

4.4K

Area of Science:

  • Materials Science
  • Semiconductor Physics
  • Electrical Engineering

Background:

  • Vertical channel-all-around (VCAA) transistors using indium-gallium-zinc oxide (IGZO) are key for 3D integration.
  • Existing IGZO VCAA FETs face challenges with contact resistance asymmetry and drive-current/leakage trade-offs due to uniform doping.

Purpose of the Study:

  • To develop a high-performance VCAA FET by engineering a vertical indium-gradient channel.
  • To address limitations in contact resistance and optimize performance for monolithic 3D integration.

Main Methods:

  • Fabrication of VCAA FETs with an in situ engineered indium-gradient channel via resputtering.
  • Characterization of device performance, including on-current and contact resistivity.
  • Development of an analytical framework to analyze contact resistances and transport mechanisms.

Main Results:

  • Achieved a record high on-current of 82.8 μA/μm.
  • Obtained an ultralow contact resistivity of 8 × 10-7 Ω·cm2.
  • Demonstrated that asymmetric Schottky barrier height and drain-induced barrier thinning drive transport behavior.

Conclusions:

  • The indium-gradient channel effectively reduces Schottky barrier height and contact resistance.
  • The study provides fundamental insights into vertical transport in oxide semiconductors.
  • Offers a scalable method for engineering contact symmetry in vertical logic devices.