Integration of Freestanding High-k Oxide Membranes for 2D Ferroelectric Field-Effect Transistors

Ferroelectric field-effect transistors (FeFETs) based on oxides with exceptional dielectric and ferroelectric properties offer compelling prospects for energy-efficient logic, nonvolatile memory, and neuromorphic computing. However, integrating high-k ferroelectrics like BaTiO₃ (BTO) with semiconductor channels remains challenging due to epitaxial growth constraints and poor complementary metal-oxide-semiconductor (CMOS) compatibility. Freestanding ferroelectric membranes offer a promising route for van der Waals (vdW) integration, yet practical implementation is impeded by issues such as mechanical deformation during transfer and defect-induced leakage. Here, a defect-tolerant strategy for top-gate integration of freestanding BTO membranes with MoS₂ channels is presented. A water-mediated release combined with polymethyl methacrylate (PMMA)-assisted transfer process is developed to preserve membrane and interface integrity, while a nanoscale dielectric-channel junction design effectively suppresses leakage current well below the low-power limit. The resulting FeFETs exhibit a record-high memory window of 0.22 V nm^-1, an ultrahigh dielectric constant of 52, and a near-ideal subthreshold swing of 60 mV dec^-1. Furthermore, a fully functional 3 × 4 top-gate FeFET array enabling in-memory logic and synaptic functionalities is demonstrated. This work establishes a scalable and transferable platform for incorporating high‑k ferroelectric oxides into high-performance reconfigurable 2D nanoelectronics.