Low power and high-speed quadrate node upset tolerant latch design using CNTFET

Area of Science:

• Semiconductor device physics
• Nanotechnology
• Integrated circuit design

Background:

• Semiconductor scaling faces challenges like reduced reliability and susceptibility to Single Event Upsets (SEUs) caused by heavy charged particles.
• Radiation Hardening by Design (RHBD) techniques are crucial for mitigating SEUs in modern integrated circuits (ICs).
• Carbon nanotubes (CNTs) offer a promising alternative to CMOS technology, potentially improving performance and reliability.

Purpose of the Study:

• To propose and investigate a novel Low power High speed Quadrate Node Upset Carbon Nanotube latch (LHQCNT).
• To enhance robustness against Multi Node Upsets through a unique design with redundant nodes.
• To compare the performance of the LHQCNT latch against existing hardened latches.

Main Methods:

• Design and simulation of the LHQCNT latch using carbon nanotube technology.
• Implementation of a delta interconnection within three Dual Interlocked cells for redundancy.
• Comparative performance analysis including power, delay, Power Delay Product (PDP), and Average Power Delay Product (APDP).

Main Results:

• The LHQCNT latch achieved remarkably low power consumption (4.4 µW) and delay (1.23 ps) at a 1V supply voltage.
• Demonstrated excellent soft error tolerance, comparable to existing hardened latches.
• Achieved low PDP (5.41e-18 J) and APDP (5.19e-2).

Conclusions:

• The proposed LHQCNT latch effectively addresses SEUs and Multi Node Upsets in scaled ICs.
• CNT technology provides a viable path for developing high-performance, reliable semiconductor circuits.
• The LHQCNT latch represents a significant advancement in low-power, high-speed, and radiation-hardened latch design.