Charge Trapping Dynamics of Nanofloating Gates in Synaptic Transistors Revealed by Genomic Simulation for...

Area of Science:

• Materials Science
• Computer Engineering
• Artificial Intelligence

Background:

• Neuromorphic hardware offers ultralow power and high parallelism, addressing the von Neumann bottleneck.
• Artificial synapses are key components, but understanding electron distribution and charge storage is difficult.
• Direct observation of microscopic electron dynamics in synaptic devices is challenging.

Purpose of the Study:

• To explore the effects of quantum dot (QD) size, concentration gradients, and carrier fields on synaptic transistor behavior.
• To understand the dynamic evolution of charge trapping in QD-based artificial synapses.
• To identify high-performance device designs through simulation-based screening.

Main Methods:

• Utilized high-throughput, high-precision simulations on quantum dot floating-gate synaptic transistors.
• Systematically investigated the interplay between QD properties and carrier concentration.
• Developed gene-performance mapping models for device design.

Main Results:

• Simulations revealed dynamic charge trapping evolution, from shallow to deep-level localized trapping, based on device genome.
• Identified optimal 'gene combinations' for high-performance device modules.
• Designed a bilayer QD array device achieving 96.95% MNIST recognition accuracy, a 4.72% improvement over monolayer structures.

Conclusions:

• High-throughput simulations are effective for understanding and optimizing charge-trapping mechanisms in synaptic devices.
• Simulation-driven design enables the development of advanced neuromorphic hardware with enhanced performance and retention.
• This approach facilitates the creation of efficient gene-performance mapping models for future neuromorphic systems.