Enhancing uniformity in HARC etching via edge bias voltage and structural impedance variations in a rectangular...

Area of Science:

• Materials Science and Engineering
• Plasma Physics and Engineering
• Semiconductor Manufacturing Technology

Background:

• Plasma etching is critical for semiconductor fabrication, enabling high aspect ratio capacitors (HARC) and complex device architectures.
• Focus ring erosion during etching degrades plasma uniformity and causes sheath distortion, leading to non-uniform etch profiles and reduced productivity.
• These issues necessitate advanced methods to maintain plasma stability and control etching processes.

Purpose of the Study:

• To investigate the effect of separated DC edge bias on plasma uniformity and ion incidence during semiconductor etching.
• To control plasma sheath potential for enhanced etching uniformity and mitigation of profile tilting.
• To optimize focus ring impedance for improved plasma stability and sheath control.

Main Methods:

• Implementation of a separated DC edge bias system to locally control plasma sheath potential at the wafer edge.
• Experimental variation of DC voltages and modification of the impedance ratio between the focus ring and wafer chuck.
• Analysis of etch profiles, uniformity, and plasma stability under different electrical biasing conditions.

Main Results:

• Localized DC voltages at the edge improved etching uniformity and mitigated profile tilting, resulting in well-defined, vertical trenches.
• DC voltages exceeding 280 V induced detrimental current flow, causing plasma instability and impaired sheath control.
• Modifying the focus ring to wafer chuck impedance ratio effectively alleviated electrical interference and etching non-uniformity.

Conclusions:

• Separated DC edge bias is a viable strategy for enhancing plasma uniformity and etch profile control in semiconductor fabrication.
• Careful management of DC voltage levels and impedance matching is crucial to avoid plasma instability.
• The proposed approach shows promise for improving etching efficiency and yield in next-generation memory device manufacturing.