Cross Comparison Between Thermal Cycling and High Temperature Stress on I/O Connection Elements

Area of Science:

• Electrical Engineering
• Materials Science
• Semiconductor Device Physics

Background:

• Field-Programmable Gate Arrays (FPGAs) are crucial in modern electronics.
• Understanding the reliability of FPGA I/O paths under stress is vital for system longevity.
• Degradation mechanisms can differ based on applied electrical and thermal stress conditions.

Purpose of the Study:

• To investigate resistance drift in FPGA I/O paths under combined electrical and thermal stress.
• To differentiate between on-die and package-level degradation mechanisms.
• To establish a foundation for reliability assessment and self-monitoring in electronic systems.

Main Methods:

• Utilized a Xilinx Spartan-6 FPGA for testing.
• Employed a multiplexed measurement approach to track resistance, voltage, and current.
• Applied accelerated stress modes: high-temperature dwell (80-120 °C) and thermal cycling (80-140 °C).

Main Results:

• Both stress modes showed sub-linear (power-law) resistance change over time.
• Arrhenius analysis revealed distinct activation energies: ~0.62 eV for dwell, ~1.3 eV for cycling.
• Lower activation energy linked to on-die degradation; higher energy to package-level thermo-mechanical damage.

Conclusions:

• Resistance drift in FPGA I/O paths effectively distinguishes between device-centric and package-centric aging.
• Findings support the development of resistance-based monitoring for electronic system reliability.
• The study provides insights into FPGA aging mechanisms for improved design and maintenance.