A High-PSRR LDO with Low Noise and Ultra-Low Power Consumption

Area of Science:

• Integrated Circuit Design
• Analog Electronics
• Power Management

Background:

• Low dropout regulator (LDO) chips are crucial for noise-sensitive applications like sensors and RF circuits.
• Existing LDO designs struggle to simultaneously achieve high power supply rejection ratio (PSRR), low output noise, and low standby current.
• These limitations restrict the use of LDOs in high-end applications.

Purpose of the Study:

• To design and fabricate a novel LDO chip that integrates high PSRR, low output noise, and low standby current.
• To overcome the limitations of existing LDO technologies for advanced electronic systems.
• To enable high-end applications requiring superior power supply characteristics.

Main Methods:

• Increased loop gain, introduced an improved feedforward path, and adopted an isolated power supply to enhance PSRR.
• Optimized the error amplifier (EA) design and incorporated a low-pass filter to reduce output voltage noise.
• Utilized a depletion process and an optimized reference structure to minimize standby power consumption without compromising accuracy.

Main Results:

• Achieved a measured PSRR of 95dB at 1 kHz and above 45 dB at 1 MHz.
• Measured integrated output noise below 5.4 μVrms (10 Hz to 100 KHz).
• Recorded a standby current of less than 400 nA at zero load current.

Conclusions:

• The designed LDO chip demonstrates excellent performance in PSRR, output noise, and standby power consumption.
• The integrated design successfully addresses the simultaneous requirements for high-end LDO applications.
• The fabricated chip, using SMIC's 0.18 μm/5 V/BCD process, validates the effectiveness of the proposed techniques.