Device and Circuit Co-Optimization of Split-Controlled Flip-Flops Against Aging Towards Low-Voltage Applications

Area of Science:

• Electrical Engineering
• Materials Science
• Computer Engineering

Background:

• Transistor downscaling intensifies aging mechanisms like bias temperature instability (BTI) and hot-carrier injection (HCI).
• These aging effects critically impact flip-flops in low-voltage integrated circuits, crucial for IoT and biomedical applications.
• Reliability challenges are significant for nanoscale integrated circuits operating at reduced supply voltages.

Purpose of the Study:

• To propose and evaluate a novel transistor-level mitigation technique for aging in low-voltage Split-Controlled Flip-Flops (SCFFs).
• To enhance the reliability and performance of SCFFs operating at ultra-low supply voltages.
• To address critical aging mechanisms within a specific 14 nm process library.

Main Methods:

• Detailed analysis of aging-critical transistors within the SCFF architecture.
• Development and implementation of three targeted enhancement strategies at the transistor level.
• Extensive simulations using a domestic 14 nm process library to validate the proposed technique.

Main Results:

• Achieved over 60% reduction in PMOS threshold voltage degradation.
• Demonstrated a 40% reduction in timing delay for the improved SCFF.
• Confirmed robust operation at a supply voltage as low as 0.4 V.

Conclusions:

• The proposed transistor-level mitigation technique effectively addresses aging effects in low-voltage SCFFs.
• The approach significantly enhances the reliability and performance of SCFFs under low-voltage conditions.
• This work provides a viable solution for extending the operational lifespan of integrated circuits in power-sensitive applications.