A broadband mismatch calibration prototype application-specific integrated circuit for time-interleaved...

Area of Science:

• Electrical Engineering
• Integrated Circuit Design
• Signal Processing

Background:

• Time-interleaved analog-to-digital converters (TIADCs) are crucial for high-speed data acquisition.
• Field-programmable gate arrays (FPGAs) are commonly used for TIADC digital calibration but present challenges in power consumption, complexity, and resource utilization.

Purpose of the Study:

• To propose a systematic design method for reducing resource consumption in TIADC systems.
• To develop a resource-efficient digital calibration filter and integrate a simplified clock generation circuit.
• To demonstrate the effectiveness of the proposed architecture for calibrating high-speed ADCs with varying resolutions.

Main Methods:

• Developed a resource-efficient digital calibration filter by analyzing filter coefficients and optimizing computational error allocation.
• Integrated a multi-phase sampling clock generation circuit with adjustable delay for simplified system implementation and timing mismatch adjustment.
• Implemented a prototype application-specific integrated circuit (ASIC) in 130 nm CMOS technology to interface with up to four 5-Gsps ADCs.

Main Results:

• Achieved over 80% reduction in area and power consumption for the digital calibration filter.
• The prototype ASIC consumes 11.5 W and effectively calibrates broadband mismatch errors in high-speed ADCs.
• Projected over 90% power reduction compared to FPGA implementations in comparable modern process nodes, with lower implementation complexity.

Conclusions:

• The proposed systematic design method significantly reduces resource consumption in TIADC systems.
• The ASIC implementation validates the effectiveness of the digital calibration filter and clock generation circuit.
• The developed approach offers a more power-efficient and less complex solution for high-speed ADC calibration compared to FPGA-based methods.