Design and performance analysis of a vertically stacked gate-all-around nanosheet FET with embedded nanocavity for

Rudra Lakshmi Prasanna1, Srinivasa Rao Karumuri2, Vakkalakula Bharath Sreenivasulu3

  • 1VLSI-Microelectronics Research Lab, Department of Electronics and Communication Engineering, Koneru Lakshmaiah Education Foundation (Deemed to Be University, Green Fields, Vaddeswaram, Andhra Pradesh, India.

Scientific Reports
|January 29, 2026
PubMed

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