Channel-engineered GAA FETs: From device to circuit perspective for Angstrom technology nodes

Area of Science:

• Semiconductor device physics and engineering.
• Advanced CMOS and RF integrated circuit design.

Background:

• Gate-all-around (GAA) field-effect transistors (FETs) are crucial for next-generation integrated circuits.
• Conventional nanosheet FETs (NS-FETs) face challenges in further performance scaling.

Purpose of the Study:

• To conduct a comprehensive device-to-circuit analysis of channel-engineered C-FETs and I-FETs.
• To benchmark their performance against conventional NS-FETs for advanced CMOS logic and RF applications.

Main Methods:

• Calibrated 3D Technology Computer-Aided Design (TCAD) simulations for devices designed to sub-3-nm International Roadmap for Devices and Systems (IRDS) guidelines.
• Device performance evaluation including drive current, scalability, and short-channel behavior.
• Analog, RF, and circuit-level simulations using LUT-based Verilog-A models.

Main Results:

• C-FETs and I-FETs with vertical inter-bridge (IB) channels show enhanced effective width and drive current compared to NS-FETs.
• I-FETs achieve the highest Ion/Ioff ratio and demonstrate superior performance and scalability with varying dimensions.
• Both C-FETs and I-FETs exhibit improved transconductance, cut-off frequency, reduced intrinsic delay, higher switching currents, and ring-oscillator frequencies.

Conclusions:

• Channel-engineered C-FET and I-FET architectures offer substantial performance advantages over NS-FETs.
• These novel FET designs are highly suitable for advanced CMOS logic and high-speed RF systems targeting angstrom technology nodes.
• The I-FET, in particular, presents a promising candidate for future high-performance integrated circuits.