A review of SPAD array chip design for direct time-of-flight LiDAR

Area of Science:

• Electrical Engineering
• Optoelectronics
• Sensor Technology

Background:

• Increasing demands for LiDAR performance necessitate advanced receiver chip designs.
• Current LiDAR systems require higher data processing volumes, ranging accuracy, and anti-interference capabilities.
• Significant transformations are occurring in LiDAR receiver chip architecture, data flow, and algorithms.

Purpose of the Study:

• To review the current design status of direct Time-of-Flight (dToF) ranging sensor chips.
• To systematically summarize innovations in ranging methods, anti-interference, accuracy optimization, and PPA design.
• To provide references for future research and development in ToF ranging sensor chips.

Main Methods:

• Review of novel ranging techniques, including histogram-free and variable histogram resolution methods.
• Analysis of anti-interference strategies: ambient light suppression and inter-LiDAR interference mitigation.
• Examination of ranging accuracy calibration methods and comprehensive chip Power, Performance, and Area (PPA) optimization.

Main Results:

• Identified two novel technical schemes for ranging: histogram-free and variable histogram resolution.
• Detailed chip-level approaches for ambient light suppression and inter-LiDAR interference mitigation.
• Highlighted comprehensive design optimization strategies for chip PPA.

Conclusions:

• Direct Time-of-Flight (dToF) sensor chips have seen significant advancements in design.
• Innovations in ranging methods and interference suppression are crucial for meeting LiDAR requirements.
• Further research is needed to address existing design bottlenecks and enhance future ToF sensor chip performance.