SUBTRACTIVE NANOFLUIDICS IN 65-NM CMOS COPPER BEOL ACHIEVE 100-NM WIDTH.

Area of Science:

• Semiconductor Manufacturing
• Nanotechnology
• Microfluidics

Background:

• Integrating microfluidic devices with standard semiconductor fabrication processes presents significant challenges.
• Existing methods for creating micro/nanoscale fluidic channels often require specialized equipment or multiple fabrication steps, increasing complexity and cost.

Purpose of the Study:

• To demonstrate the first implementation of 100-nm-wide nanofluidics integrated into a commercial 65-nm CMOS chip.
• To develop a fabrication method compatible with standard CMOS back-end-of-line (BEOL) processing.
• To establish a non-destructive characterization technique for sub-wavelength fluidic structures.

Main Methods:

• Utilized a one-step wet-etch process to remove copper interconnects from the BEOL.
• Employed continuous monitoring of transistor characteristics (I_DS-V_GS) to ensure device integrity during etching.
• Successfully etched vertical fluidic channels through 360 nm × 360 nm vias.
• Developed a non-destructive laser microscopy technique for imaging channels smaller than the wavelength of visible light.

Main Results:

• Achieved 100-nm-wide nanofluidic channels within a 65-nm CMOS chip.
• Demonstrated the feasibility of vertical fluidics through etched vias.
• Verified transistor integrity was maintained throughout the fabrication process.
• Successfully imaged sub-wavelength fluidic channels using the novel laser microscopy technique.

Conclusions:

• The presented one-step wet-etch method is a viable approach for integrating nanofluidics into standard CMOS technology.
• This integration opens possibilities for novel lab-on-chip devices and advanced sensor applications.
• The developed imaging technique provides essential characterization capabilities for sub-wavelength nanostructures.