SEU-Hardened High-Speed SRAM Design with Self-Refresh and Adjacent-Bit Error Correction

Area of Science:

• Electrical Engineering
• Computer Architecture
• Reliability Engineering

Background:

• Radiation-prone environments pose significant risks to electronic components, particularly memory systems.
• Single-event upsets (SEUs) can cause data corruption in static random access memory (SRAM).
• Existing error correction codes (ECC) may not offer sufficient protection or efficiency for high-speed applications.

Purpose of the Study:

• To propose a novel high-speed SRAM architecture with enhanced resilience against SEUs.
• To integrate a self-refresh mechanism with a single error and adjacent-bit errors correction (SEABEC) scheme.
• To evaluate the performance, area, and power overhead of the proposed architecture.

Main Methods:

• Implementation of a novel SEABEC scheme using extended Hamming coding.
• Integration of dynamic circuits and a self-refresh mechanism.
• Radiation experiments using a variable Linear Energy Transfer (LET) range (1.63-21.8 MeV·cm²/mg).

Main Results:

• Achieved a 29.1% read-write speed improvement.
• Reduced SEU cross-section by one order of magnitude.
• Demonstrated nearly doubled SEU resilience compared to conventional SEC-DED-based designs.
• Observed ~14.2% overall chip area increase and a 95.2% dynamic power increase for the ECC module.

Conclusions:

• The proposed SRAM architecture offers superior SEU tolerance and improved speed.
• The SEABEC scheme effectively enhances reliability in radiation-prone environments.
• This design presents a viable solution for high-reliability applications in space electronics and advanced processors.