A CNTFET based process variation resilient SRAM design for stable low power and half select free operation

Area of Science:

• Electrical Engineering
• Materials Science
• Computer Engineering

Background:

• Nanoscale static random-access memory (SRAM) designs face challenges in stability, power, and process variation sensitivity at low voltages.
• Existing SRAM architectures struggle to meet the demands of modern low-power integrated circuits.

Purpose of the Study:

• To propose a robust and energy-efficient carbon nanotube field-effect transistor (CNTFET)-based 9T SRAM cell architecture.
• To optimize the design for low-voltage operation and enhanced noise immunity.

Main Methods:

• A novel 9T SRAM cell architecture with a fully decoupled read/write structure and single-ended access was designed.
• HSPICE simulations using a 32-nm CNTFET model were performed at a 0.3V supply voltage.
• Monte Carlo simulations were used to assess robustness against process variations.

Main Results:

• The proposed 9T SRAM cell demonstrated a 2.1x improvement in read static noise margin (RSNM) and a 14x enhancement in write static noise margin (WSNM) over conventional 6T SRAM.
• Significant reductions in read, write, and leakage power were achieved.
• Superior robustness against process variations was confirmed, with high mean-to-standard-deviation ratios for RSNM and WSNM.

Conclusions:

• The CNTFET-based 9T SRAM cell offers a balanced solution for low-voltage, energy-constrained, and variability-aware memory systems.
• The design presents a promising candidate for future integrated circuits utilizing CNTFET technology.
• The architecture achieves improved performance with only a modest area overhead.