System-level FPGA validation of a trainable and robust multiplier-free spiking neural network

Area of Science:

• Neuromorphic Engineering
• Artificial Intelligence Hardware
• Spiking Neural Networks

Background:

• Large-scale AI models face hardware deployment challenges due to high computational and energy demands.
• Spiking neural networks (SNNs) offer an energy-efficient, event-driven alternative inspired by biological processing.

Purpose of the Study:

• To present a system-level FPGA validation of a trainable, multiplier-free SNN.
• To demonstrate on-chip supervised learning capabilities under fixed-point constraints.
• To evaluate the system's performance, power consumption, and noise robustness.

Main Methods:

• Implementation of a sensitive-noise threshold (SNT) mechanism.
• Integration of a limited remote supervised method (LReSuMe).
• System validation on a Xilinx ZCU104 FPGA platform with fixed-point arithmetic.

Main Results:

• Achieved high throughput and significantly low power consumption.
• Demonstrated preserved robustness against noise.
• Weight visualization revealed structured and interpretable learning patterns.

Conclusions:

• The developed SNN system offers an efficient and reliable hardware solution for neuromorphic computing.
• On-chip supervised learning is feasible under fixed-point constraints using the proposed SNN design.
• The findings support the viability of hardware-based neuromorphic systems for practical AI applications.