Channel-engineered GAA FETs: From device to circuit perspective for Angstrom technology nodes

This work presents a comprehensive device-to-circuit analysis of channel-engineered gate-all-around (GAA) FETs intended for advanced CMOS logic applications, namely the comb-shaped FET (C-FET) and inter-bridge FET (I-FET), benchmarked against a conventional nanosheet FET (NS-FET). All devices are designed according to sub-3-nm IRDS guidelines and evaluated through calibrated 3D TCAD simulations. The results show that the incorporation of vertical inter-bridge (IB) channels in C-FET and I-FET significantly enhances the effective width, leading to notable improvements in drive current, with the I-FET achieving the highest [Formula: see text] and [Formula: see text] ratio. Scalability studies reveal that the I-FET retains superior performance under variations in gate length and IB dimensions while maintaining acceptable short-channel behavior. Analog and RF evaluations indicate that both C-FET and I-FET exhibit enhanced transconductance, cut-off frequency, and reduced intrinsic delay compared to NS-FETs, making them promising candidates for high-speed applications. Circuit-level simulations using LUT-based Verilog-A models further confirm that C-FET and I-FET deliver higher switching currents and improved ring-oscillator frequencies, with the I-FET achieving the maximum [Formula: see text] across all supply voltages and stage counts. Overall, the results demonstrate that channel-engineered C-FET and I-FET architectures provide substantial performance advantages over conventional nanosheet devices, highlighting their suitability for advanced CMOS and RF systems for angstrom technology nodes.