Single and Repetitive Surge Reliability of 1200 V Asymmetric Trench SiC MOSFETs Under Various Gate Biases

The parameter degradation and failure mechanisms of 1200 V asymmetric trench-type (AT) silicon carbide (SiC) metal oxide semiconductor field-effect transistors (MOSFETs) under various single and repetitive surge currents, with various gate bias voltages (V_GS) of 0 V, -5 V, and -10 V, are systematically investigated in this work. It is indicated that V_GS has no impact on the single surge reliability, with the same maximum single surge current (SSC_max) under different V_GS. However, during repetitive surge stress (90% and 60% SSC_max), the maximum surge cycles have increased as V_GS increases from -10 V to 0 V. It may be caused by the enhancement of channel-assisted leakage conduction, allowing more surge current to flow through the channel. It is concluded from gate capacitance (Cg-Vg) and low-frequency noise (LFN) characterizations that lower V_GS increases SiC/SiO₂ interface defect density, accelerating parameter degradation during single and repetitive surge stress. Both chip and package failures are observed for single and repetitive surge stress. For single surge stress, the device failure has resulted from the melted source Al as the metal erodes and penetrates through the interlayer dielectric and the ohmic contact layer between the source metal and the SiC-doped region, respectively, leading to a three-terminal short circuit. For repetitive surge stress, the device failure has been caused by the penetration of Al metal into the interlayer dielectric, leading to a gate-source short circuit. This comprehensive research provides valuable guidance for enhancing the surge reliability of SiC MOSFETs.