Exploring the Feasibility of Deploying Future SDR Applications on RFSoC FPGA Device

Software-defined radio (SDR) has become a critical technology in modern communications, offering the flexibility and programmability required for dynamic signal processing. As the demand for high-performance SDR systems continues to increase, selecting an appropriate hardware platform has become increasingly important. This paper investigates the implementation of a state-of-the-art Chessboard-based Automatic Modulation Classification (CAMC) algorithm on a Field-Programmable Gate Array (FPGA)-based RFSoC platform, exploring various parallel datapath architectures and their impact on performance. The relationships between maximum operating frequency, bandwidth, and resource consumption are evaluated as the number of parallel instances and peripheral configurations are varied. The results show that the parallel CAMC design, incorporating all required peripherals, achieves a bandwidth of 29.0 GBps while consuming 82.31% of lookup tables (LUTs) and 50.67% of flip-flops (FFs), whereas the datapath-only design achieves a bandwidth of 24.8 GBps with significantly lower resource consumption. In addition, as the number of parallel instances increases, the number of High-Performance (HP) ports or master ports increases, the maximum operating frequency decreases, and bandwidth growth gradually saturates. The presented implementation study and open-source hardware designs provide practical reference architectures for evaluating the trade-offs between bandwidth, performance, and resource utilisation in FPGA-based SDR systems.