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Updated: Aug 28, 2026

A Fabrication and Measurement Method for a Flexible Ferroelectric Element Based on Van Der Waals Heteroepitaxy
Published on: April 8, 2018
Ferroelectric Hafnium Oxide for In-Memory Computing: Advancing Devices, Circuit Architectures, and System-Level
Chengyu He1, Wei Li1, Jianjun Li1
1The State Key Laboratory of Electronic Thin Films and Integrated Devices, School of Integrated Circuit Science and Engineering, University of Electronic Science and Technology of China, Chengdu 611731, China.
Abstract:
Data movement has become a dominant bottleneck in modern artificial intelligence hardware, making in-memory computing a critical direction for energy-efficient and memory-centric architectures. Ferroelectric hafnium oxide provides a distinctive materials platform for this transition because field-driven polarization switching, non-volatility, CMOS compatibility, and nanoscale thickness scalability can be combined within a process-relevant oxide system. This review establishes a device-to-system perspective on HfO2-based and Hf0.5Zr0.5O2-based ferroelectric memories for in-memory computing. Instead of treating ferroelectric materials, memory devices, circuit primitives, and computing architectures as separate research topics, we examine how their mutual constraints define the achievable efficiency, precision, reliability, and scalability of hafnia-based computing systems. The discussion connects polarization engineering and defect control with charge-domain computation, threshold-state logic, associative search, analog weight representation, neuromorphic plasticity, and sensor-side processing. Particular emphasis is placed on the translation of ferroelectric functionality from individual devices to arrays, macros, and system-level accelerators. We identify variability, fatigue, charge trapping, multilevel-state uncertainty, peripheral overhead, and benchmarking inconsistency as the central barriers that prevent device-level advantages from directly becoming system-level gains. Finally, we outline a cross-layer roadmap in which ferroelectric stack engineering, variability-tolerant arrays, precision-scalable architectures, and SoC-level integration are co-optimized to enable reliable HZO-based memory-centric computing.
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