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Published on: May 13, 2020
Trap-Controlled Multi-Level Switching in In-Doped GeSbSe for Selector-Only Memory
Won Hee Jeong1, Min Kyu Yang2, Gun Hwan Kim1,3
1Department of System Semiconductor Engineering, Yonsei University, Seoul03722, Republic of Korea.
Abstract:
Selector-only memory (SOM) based on ovonic threshold switching (OTS) is an attractive platform for high-density memory architectures because it combines a simple device stack with volatile conduction switching and a nonvolatile threshold voltage (Vth). However, multibit operation has remained challenging due to the lack of verifying schemes capable of discriminating multiple Vth levels without destructive readout. Here, multibit Vth programming in SOM is achieved by engineering the amplitude and width of programming pulses, producing well-separated threshold states within a practical memory window. To enable reliable state discrimination, two SOM-specific verifying strategies are introduced. Subthreshold current verification distinguishes programmed states using a voltage below the lowest Vth by comparing preswitching currents. Compliance-limited reference verification adopts a boundary-voltage concept inspired by NAND flash while enforcing current compliance to suppress threshold switching (TS) and prevent state perturbation. Together, these approaches enable stable and repeatable multibit operation while preserving the programmed Vth distribution. Furthermore, the discrete and noncumulative Vth states enable deterministic finite-state-machine (FSM) functionality, where sequential electrical inputs are mapped to distinct state trajectories. This trajectory-based operation establishes SOM as both a viable multibit memory and a compact hardware primitive for sequential information processing.
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