Steep-Slope MoS2 and WSe2 Field-Effect Transistors Enabled by Ag/SiO2 Atomic Threshold Switches for...

Reducing power consumption in complementary metal-oxide-semiconductor (CMOS) logic is fundamentally limited by thermionic carrier transport in conventional field-effect transistors (FETs). Although steep-slope devices have been widely investigated, inverter-level demonstrations of atomic threshold-switching FET architectures-particularly in complementary configurations-remain scarce. Here, we report the first experimental demonstration of steep-slope CMOS devices enabled by the monolithic integration of atomic threshold switches (ATS) with both n-type MoS2 and p-type WSe2 FETs. We further implement the first CMOS inverter architecture based on this steep-slope CMOS platform and characterize its electrical performance. Owing to the abrupt voltage redistribution across the transistor-ATS stack, the ATS-integrated MoS2 and WSe2 FETs exhibit an apparent subthreshold swing below 5 mV·dec-1, while simultaneously benefiting from reduced static power consumption due to the intrinsically low OFF-state leakage current of the ATS. When incorporated into steep-slope CMOS devices with the ATS selectively placed in the pull-up branch, the resulting inverter achieves static-power reduction while maintaining stable inverter-like operation in the quasi-logic regime. While recovering the switching speed involves an inherent trade-off with dynamic power, circuit-level simulations indicate that engineered ATS integration reliably preserves the static-power benefit under matched logic performance.