Ab initio quantum transport simulation of sub-5 nm monolayer SnTe field-effect transistors

As traditional silicon transistors approach their physical scaling limits, semiconductor progress increasingly emphasizes time-scaling (τ-law). Under the τ-law paradigm, two-dimensional materials inherently suppress parasitic capacitance due to their atomic-scale channels, thereby achieving low delay time at ultimate physical dimensions. Herein, we have simulated sub-5 nm gate length (L_g) monolayer (ML) SnTe metal-oxide-semiconductor field-effect transistors using ab initio quantum transport simulations. The 1 nm L_g p-type (armchair-directed) device shows an ultra-low power-delay product of 0.0026 fJ µm^-1, corresponding to just 1% of the International Roadmap for Devices and Systems (IRDS) high-performance targets. Furthermore, when evaluating the energy-delay product, the 1 nm L_g ML SnTe MOSFET exhibits a significant advantage over other tellurium-based counterparts (tellurene and MoTe₂) and the isostructural GeSe. Our findings suggest that ML SnTe is a promising candidate for future time-scaling, energy-efficient post-silicon electronic devices.