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Nanoscale Research Letters|April 21, 2016
Vertical Silicon Nanowire Field Effect Transistors with Nanoscale Gate-All-AroundYoussouf Guerfi, Guilhem LarrieuNanotechnology|November 16, 2013
Modelling and engineering of stress based controlled oxidation effects for silicon nanostructure patterningXiang-Lei Han, Guilhem Larrieu, Christophe KrzeminskiJournal of Nanoscience and Nanotechnology|December 9, 2010
Realization of vertical silicon nanowire networks with an ultra high density using a top-down approachXiang-Lei Han, Guilhem Larrieu, Emmanuel DuboisNature Nanotechnology|January 22, 2019
Pushing the limits of optical information storage using deep learningPeter R Wiecha, Aurélie Lecestre, Nicolas Mallet, et al.ACS Omega|February 28, 2022
Large-Scale Monolithic Fabrication of III-V Vertical Nanowires on a Standard Si(100) Microelectronic SubstrateAurélie Lecestre, Mickael Martin, Filadelfo Cristiano, et al.Advanced Materials (Deerfield Beach, Fla.)|June 29, 2023
Combining PEDOT:PSS Polymer Coating with Metallic 3D Nanowires Electrodes to Achieve High Electrochemical Performances for Neuronal Interfacing ApplicationsInes Muguet, Ali Maziz, Fabrice Mathieu, et al.ACS Nano|July 31, 2025
Engineering Ni-Silicide Nanocontacts for 3D Silicon Devices via Geometrical Confinement ControlJonas Müller, Remi Demoulin, Leonardo Cancellara, et al.Nano Letters|June 17, 2024
Logic Gates Based on 3D Vertical Junctionless Gate-All-Around Transistors with Reliable Multilevel Contact EngineeringAbhishek Kumar, Jonas Müller, Sylvain Pelloquin, et al.Small (Weinheim an Der Bergstrasse, Germany)|March 2, 2026
Monolithic 3D Nanoelectrode Arrays on CMOS Circuitry for Scalable, High-Resolution Neural RecordingAziliz Lecomte, Laurent Mazenq, Marie-Charline Blatché, et al.Nature Nanotechnology|November 8, 2016
Evolutionary multi-objective optimization of colour pixels based on dielectric nanoantennasPeter R Wiecha, Arnaud Arbouet, Christian Girard, et al.Pageof 3