Jove
Visualize
Contact Us
JoVE
x logofacebook logolinkedin logoyoutube logo
ABOUT JoVE
OverviewLeadershipBlogJoVE Help Center
AUTHORS
Publishing ProcessEditorial BoardScope & PoliciesPeer ReviewFAQSubmit
LIBRARIANS
TestimonialsSubscriptionsAccessResourcesLibrary Advisory BoardFAQ
RESEARCH
JoVE JournalMethods CollectionsJoVE Encyclopedia of ExperimentsArchive
EDUCATION
JoVE CoreJoVE BusinessJoVE Science EducationJoVE Lab ManualFaculty Resource CenterFaculty Site
Terms & Conditions of Use
Privacy Policy
Policies

Filters

Sreehari Veeramachaneni

Showing results (1-10 of 3) with videos related to

Pageof 1
Sort By:
Scientific Reports|July 2, 2025
Design of a low-delay 4-bit parallel prefix adder using QCA technologyTushar Niranjan, Anirban Nayak, Sreehari Veeramachaneni, et al.
Scientific Reports|April 21, 2025
Mitigating side channel attacks on FPGA through deep learning and dynamic partial reconfigurationSesibhushana Rao Bommana, Sreehari Veeramachaneni, Syed Ershad, et al.
Scientific Reports|January 20, 2023
Efficient design and analysis of secure CMOS logic through logic encryptionSai Srinivas Chandra, R Jagadeesh Kannan, B Saravana Balaji, et al.
Pageof 1

Showing results (1-10 of 3) with videos related to

Sort By:
Pageof 1
Scientific Reports|July 2, 2025
Design of a low-delay 4-bit parallel prefix adder using QCA technologyTushar Niranjan, Anirban Nayak, Sreehari Veeramachaneni, et al.
Scientific Reports|April 21, 2025
Mitigating side channel attacks on FPGA through deep learning and dynamic partial reconfigurationSesibhushana Rao Bommana, Sreehari Veeramachaneni, Syed Ershad, et al.
Scientific Reports|January 20, 2023
Efficient design and analysis of secure CMOS logic through logic encryptionSai Srinivas Chandra, R Jagadeesh Kannan, B Saravana Balaji, et al.
Pageof 1