在3D NAND闪存内存中进行Z干扰改进的新型程序方案
Jianquan Jia1,2, Lei Jin1,2, Xinlei Jia1,2
1Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China.
Micromachines
|July 8, 2023
概括
3D NAND闪存中的Z干扰随着缩放而恶化. 一种新的编程方法通过降低相邻电池通路电压来减少这种干扰,显著提高了缩放设备的可靠性.
科学领域:
- 半导体设备物理 半导体设备物理
- 材料科学 材料科学 材料科学
背景情况:
- 细胞对细胞的z干扰是3DNAND充电陷内存的关键可靠性问题,由缩小的门长度 (Lg) 和门间距长度 (Ls) 加剧.
- 这种现象对3D NAND技术的持续扩展构成了重大挑战.
研究的目的:
- 研究3D NAND闪存中的编程操作期间z干扰的潜在机制.
- 提出并验证一种新的编程方案,以减轻z干扰并提高细胞可靠性.
主要方法:
- 利用技术计算机辅助设计 (TCAD) 模拟来建模和分析z干扰机制.
- 采用数据验证来确认模拟结果并评估拟议方案的有效性.
主要成果:
- 识别了在编程过程中调节的细胞间被困电荷,作为z干扰的关键贡献者.
- 通过降低相邻电池的通行电压 (Vpass),拟议的方案在Lg/Ls = 31/20 nm的擦除电池中实现了40.1%的值电压 (Vth) 转移的抑制.
- 分析提供了关于优化程序干扰和z干扰之间的平衡的见解,用于缩放的Lg-Ls.
结论:
- 这种新的编程方案有效地抑制了3D NAND闪存中的z干扰.
- 这种方法提供了一个可行的解决方案,可以提高缩放的3D NAND设备的可靠性.
- 进一步的分析支持对未来NAND闪存扩展的编程策略进行优化.
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