Sample preparation for precise and quantitative electron holographic analysis of semiconductor devices

Area of Science:

• Materials Science
• Solid State Physics
• Nanotechnology

Background:

• Precise electrostatic potential analysis is crucial for understanding semiconductor device behavior.
• Traditional sample preparation methods like ion milling can introduce artifacts.
• Off-axis electron holography offers high-resolution electrostatic potential mapping.

Purpose of the Study:

• To develop and validate a wedge polishing technique for preparing silicon (Si) n-p junction and p-channel metal-oxide-silicon field-effect transistor (pMOSFET) samples.
• To enable quantitative electrostatic potential analysis using off-axis electron holography.
• To investigate the effect of sample thickness on the reliability of holographic measurements.

Main Methods:

• Wedge polishing using colloidal silica suspension for final thinning to avoid ion milling artifacts.
• Off-axis electron holography for electrostatic potential analysis.
• Conventional transmission electron microscopy for cross-verification of dimensions.

Main Results:

• The developed wedge polishing method produced samples with uniform thickness and no significant charging, confirmed by electron holography.
• A minimum sample thickness of approximately 160 nm was identified as necessary for reliable electrostatic potential measurements.
• Quantitative analysis of a pMOSFET sample revealed a 16 nm difference between metallurgical and actual gate lengths due to junction encroachment.

Conclusions:

• Wedge polishing is a suitable artifact-free technique for preparing Si devices for quantitative electrostatic potential analysis via electron holography.
• Accurate determination of device dimensions, such as gate length and junction encroachment, is achievable.
• Understanding the relationship between sample thickness and measurement accuracy is vital for reliable nanoscale electrostatic analysis.