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Grain-size considerations for optoelectronic multistage interconnection networks.

A V Krishnamoorthy, P J Marchand, F E Kiamilev

|August 25, 2010

Summary

This study finds an optimal grain size for optoelectronic networks, balancing performance and cost. Larger grain sizes reduce performance, while smaller ones increase cost, with a sweet spot for efficient design.

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Area of Science:

Computer Engineering
Optical Engineering
VLSI Design

Background:

Multistage Interconnection Networks (MINs) are crucial for parallel computing.
Optoelectronic interconnects offer potential advantages over purely electronic systems.
Balancing performance and cost in optoelectronic MINs requires careful design considerations.

Purpose of the Study:

To investigate the performance-cost trade-off of optical versus electronic interconnects in optoelectronic MINs.
To analyze a specific packet-switched, free-space shuffle-exchange MIN architecture.
To determine the optimal grain size for maximizing performance per unit cost.

Main Methods:

Detailed design and analysis of a 2-D optoelectronic shuffle-exchange routing network with variable grain size (K).
System bandwidth as the performance metric; system area, power, and volume as cost metrics.
Evaluation of technology parameters (hologram phase levels, modulator voltage, detector power, VLSI size) and architectural modifications.

Main Results:

An optimal range of grain sizes exists, balancing performance and cost.
Grain sizes > 256x256 reduce performance; < 16x16 increase cost.
For 4096 channels, optimal grain size is ~250-400 transistors/channel.
Decreasing VLSI feature size increases optimum grain size; improved optical performance may reduce it.

Conclusions:

Optoelectronic MINs offer a wide range of performance/cost alternatives.
The studied architectures outperform purely electronic MINs.
Architectural modifications can increase bandwidth but may decrease performance/cost ratio.