A hybrid intelligent controller for a twin rotor MIMO system and its hardware implementation.

Area of Science:

• Control Systems Engineering
• Robotics
• Artificial Intelligence

Background:

• The Twin Rotor MIMO System (TRMS) presents a complex control challenge due to its cross-coupled dynamics.
• Precise attitude control (pitch and azimuth angles) is crucial for TRMS applications.
• Traditional PID controllers often require extensive tuning for optimal performance in complex systems.

Purpose of the Study:

• To develop and implement an advanced control strategy for the TRMS.
• To achieve fast and accurate setpoint control of both pitch and azimuth angles simultaneously.
• To optimize controller parameters for reduced error and control energy consumption.

Main Methods:

• A fuzzy PID control scheme incorporating a fuzzy compensator was designed.
• A real-valued genetic algorithm (RGA) was employed to tune the parameters of four independent 2-DOF PID controllers.
• The Integral of Time multiplied by the Square Error (ITSE) criterion was used as the fitness function for the RGA.
• A novel RGA method was investigated for optimizing over 10 parameters.
• A hardware-in-the-loop (HIL) system was implemented using a Xilinx Spartan II SP200 FPGA and VHDL for real-time control.

Main Results:

• The proposed fuzzy PID control scheme effectively controlled the TRMS to desired attitudes.
• The RGA successfully optimized the controller parameters, leading to reduced system error and control energy.
• The ITSE criterion proved effective as a fitness function for the RGA.
• The investigation into a new RGA method for numerous parameters showed promise.
• The FPGA-based HIL system enabled real-time validation of the control strategy.

Conclusions:

• The fuzzy PID control scheme optimized by RGA offers a robust and efficient solution for TRMS control.
• The integration of fuzzy logic and genetic algorithms enhances control performance.
• The developed method is suitable for real-time implementation on embedded systems like FPGAs.