An improved equivalent simulation model for CMOS integrated Hall plates

Area of Science:

• Electrical Engineering
• Semiconductor Device Physics
• Microelectronics

Background:

• Existing Hall plate models lack accuracy in representing non-linear and environmental effects.
• Accurate simulation models are crucial for designing reliable Hall effect sensors in integrated circuits.

Purpose of the Study:

• To develop an improved equivalent simulation model for CMOS-integrated Hall plates.
• To incorporate voltage-dependent non-linear effects, geometrical influences, temperature variations, and packaging stress.
• To create a model with a simple structure and minimal physical/technological parameters.

Main Methods:

• Developed a novel equivalent circuit model comprising passive networks, non-linear resistances, controlled voltage sources, and parasitic capacitances.
• Implemented the model using Verilog-A hardware description language.
• Validated the model's performance using the Cadence Spectre simulator.

Main Results:

• The new model successfully simulates CMOS-integrated Hall plates.
• It accurately accounts for voltage-dependent non-linearities, geometry, temperature, and stress.
• Simulation outcomes closely match established experimental results from literature.

Conclusions:

• The proposed Hall plate model offers enhanced accuracy and simplicity for CMOS integrated circuits.
• It provides a valuable tool for the design and analysis of Hall effect sensors.
• The model's ability to include various physical influences makes it versatile for different applications.