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Tunable catalytic alloying eliminates stacking faults in compound semiconductor nanowires
Hoseok Heo1, Kibum Kang, Donghun Lee
1Division of Advanced Materials Science Science (WCU), Pohang University of Science and Technology (POSTECH), San 31, Hyoja-Dong, Nam Gu, Pohang, Gyungbuk 790-784, Korea.
Nano Letters
|January 25, 2012
Summary
Planar defect-free semiconductor nanowires were synthesized using tunable alloying. This method enables precise control over electronic and optical properties for visible light applications.
Area of Science:
- Materials Science
- Nanotechnology
- Semiconductor Physics
Background:
- Planar defects like twin and stacking faults are common in semiconductor nanowires (NWs), hindering electron transport and light emission.
- These defects arise during catalytic growth of compound semiconductors (III-V and II-VI).
Purpose of the Study:
- To develop a simple synthetic route for planar defect-free II-VI semiconductor nanowires.
- To demonstrate tunable electronic and optical properties through alloying.
Main Methods:
- Utilized tunable alloying of Cadmium (Cd) and Zinc (Zn) in Gold (Au) catalysts for synthesizing Cd(1-x)Zn(x)Te nanowires (NWs).
- Investigated the effect of eutectic alloying on interfacial stability and crystal structure during catalytic growth.
Main Results:
- Achieved planar defect-free II-VI nanowires via tunable alloying.
- Eutectic alloying of Cd and Zn in Au catalysts minimized interfacial instability, promoting homogeneous zinc blende crystal formation.
- Demonstrated intrinsic energy band gap modulation in Cd(1-x)Zn(x)Te NWs across the visible spectrum.
Conclusions:
- Tunable alloying offers a viable strategy for fabricating defect-free semiconductor nanowires.
- Cd(1-x)Zn(x)Te NWs exhibit tunable band gaps, enabling applications in light detection and emission across the visible range.
