Interface analysis of embedded chip resistor device package and its effect on drop shock reliability.

Area of Science:

• Materials Science
• Electrical Engineering
• Reliability Engineering

Background:

• Embedded passive components are crucial in modern electronics.
• Reliability under mechanical stress, like drop impacts, is vital for these components.
• Understanding intermetallic compound (IMC) formation at interfaces is key to predicting failure.

Purpose of the Study:

• To investigate the drop reliability of embedded passive packages under JESD22-B111 conditions.
• To analyze the formation and transformation of intermetallic phases at the via interface.
• To correlate simulated stress distribution with experimental drop failure locations.

Main Methods:

• Investigated chip resistors embedded in a PCB with copper plating.
• Analyzed intermetallic phase formation (Cu-Sn-Ni) after reflow and aging.
• Performed drop shock simulations based on JEDEC standards and material properties.
• Compared simulation results with experimental failure analysis.

Main Results:

• Complex intermetallic phases (Cu, Ni)6Sn5, (Cu, Ni)3Sn, and (Ni, Cu)3Sn2 formed at the via interface.
• Excessive intermetallic layer growth was not observed due to the small tin layer.
• Drop failures initiated at the intermetallic compound (IMC) interface.
• Intermetallic phase transformation due to copper diffusion altered crack starting points.
• Experimental failure locations matched simulation predictions.

Conclusions:

• Intermetallic phase transformation significantly impacts failure mechanisms in embedded passive packages under drop stress.
• The study provides valuable insights into the reliability of embedded passive components, particularly concerning mechanical shock.
• Accurate simulation of stress distribution, considering IMC evolution, is essential for predicting and improving the drop reliability of these packages.