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Efficient VLSI architecture for training radial basis function networks.

Zhe-Cheng Fan1, Wen-Jyi Hwang

  • 1Department of Computer Science and Information Engineering, National Taiwan Normal University, Taipei 116, Taiwan. a205152@hotmail.com

Sensors (Basel, Switzerland)
|March 23, 2013
PubMed
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This study introduces a new VLSI architecture for training radial basis function (RBF) networks, incorporating fuzzy C-means (FCM) and recursive Least Mean Square (LMS) operations for efficient real-time processing.

Area of Science:

  • Computer Engineering
  • Artificial Intelligence
  • Machine Learning

Background:

  • Radial Basis Function (RBF) networks are widely used for classification and regression tasks.
  • Efficient training of RBF networks is crucial for real-time applications.
  • Existing training methods can be computationally intensive.

Purpose of the Study:

  • To present a novel VLSI architecture for accelerating the training of RBF networks.
  • To integrate Fuzzy C-Means (FCM) and recursive Least Mean Square (LMS) operations within a single architecture.
  • To enable real-time training and classification using hardware acceleration.

Main Methods:

  • Designed a VLSI architecture incorporating dedicated circuits for FCM and recursive LMS.
  • Implemented the architecture using a Field Programmable Gate Array (FPGA).

Related Experiment Videos

  • Integrated the FPGA into a System on Programmable Chip (SOPC) for hardware acceleration.
  • Main Results:

    • The proposed architecture effectively trains the centers (hidden layer) using FCM.
    • The architecture efficiently trains the connecting weights (output layer) using recursive LMS.
    • Hardware implementation demonstrated feasibility for real-time RBF network training.

    Conclusions:

    • The novel VLSI architecture offers a significant improvement in RBF network training speed.
    • This architecture is a viable solution for applications demanding fast and efficient RBF training.
    • The integrated FCM and LMS circuits provide a comprehensive hardware accelerator for RBF networks.