A 0.7-V 17.4- μ W 3-lead wireless ECG SoC

Area of Science:

• Biomedical Engineering
• Integrated Circuit Design
• Wearable Technology

Background:

• Wireless body sensor networks require highly integrated, low-power solutions for continuous health monitoring.
• Existing electrocardiogram (ECG) systems often face limitations in power consumption and integration for wearable applications.

Purpose of the Study:

• To present a fully integrated, sub-1 Volt, 3-lead wireless ECG System-on-Chip (SoC).
• To achieve ultra-low power consumption for wireless body sensor network applications.

Main Methods:

• Designed a System-on-Chip (SoC) integrating a two-channel ECG front-end, driven-right-leg circuit, 8-bit SAR ADC, 16-bit microcontroller, 16 kb SRAM banks, and MICS band transceiver.
• Implemented the SoC using a 0.13-μm CMOS process, enabling sub-/near-threshold operation for microcontroller and SRAM blocks.
• Operated the entire SoC at a single 0.7-V supply.

Main Results:

• The microcontroller demonstrated exceptional energy efficiency, consuming 2.62 pJ per instruction at 0.35 V.
• Both microcontroller and memory blocks operated reliably down to 0.25 V.
• Achieved minimal power consumption: 17.4 μW in heart rate detection mode and 74.8 μW in raw data acquisition mode (500 Hz sampling rate).

Conclusions:

• The developed wireless ECG SoC offers state-of-the-art performance in terms of power efficiency and integration for biomedical applications.
• The sub-1 V operation and ultra-low power consumption make it a leading solution for next-generation wireless body sensor networks.