FPGA-Based Pulse Pile-Up Correction With Energy and Timing Recovery.

Area of Science:

• Medical Imaging
• Digital Signal Processing
• Embedded Systems

Background:

• Modern field programmable gate arrays (FPGAs) offer high clock rates and cost-effectiveness for complex signal processing.
• FPGAs are increasingly integrated into data acquisition systems for advanced scientific instruments.
• Positron emission tomography (PET) scanners require sophisticated front-end electronics for high-resolution imaging.

Purpose of the Study:

• To develop and implement an all-digital pulse pile-up correction algorithm for FPGA-based PET scanners.
• To leverage FPGA capabilities for enhanced signal processing in PET data acquisition.
• To improve the performance of small-animal PET scanners by mitigating data loss due to signal overlap.

Main Methods:

• An all-digital pulse pile-up correction algorithm was designed and implemented on an FPGA.
• The algorithm utilizes a reference pulse to extract timing and energy information from overlapping scintillation signals.
• Data was acquired using a Zecotech Photonics MAPD-N detector with an LFS-3 scintillator.

Main Results:

• The developed FPGA algorithm effectively corrects for pulse pile-up events.
• Accurate timing and energy information was successfully extracted despite signal overlap.
• The solution requires a moderate amount of FPGA resources, demonstrating efficiency.

Conclusions:

• FPGA-based signal processing is a viable approach for enhancing PET scanner performance.
• The all-digital pulse pile-up correction algorithm enables higher count rates and reduces data loss.
• This technique contributes to producing higher quality images from small-animal PET scanners.