Threshold voltage instability mechanisms of nitride based charge trap flash memory--a review

Technological scaling of charge trap device has become significantly more challenging due to two major physical limits revealed by International Technology Roadmap for Semiconductors (ITRS) 2011, i.e., (1) neighboring bit interference due to consistent shrinking in design floor space; (2) balancing act of ensuring sufficient number of electrons in shrinking storage layer to maintain stable threshold voltage (V(t)) against various V(t) instability mechanisms. Nitride based charge trap flash (CTF) is one of the better candidates to replace floating gate (FG) flash as the mainstream flash memory technology due to its inherent immunity to point defects and better device scalability. However, post cycled V(t) instability in the form of V(t) distribution shift and broadening of programmed/erased cells is still genuine reliability concerns for nitride based CTF devices. This is because the shift and broadening of V(t) distribution could degrade the operating window and thus caused premature failures of the devices. V(t) instability of nitride based CTF memory inevitably introduces statistical fluctuations in V(t) distribution of nitride based CTF which is detrimental to its long-term data retention performance. The scope of this review paper focuses on critical reliability challenges of future development of nitride based CTF development with emphasis on cell level V(t) instability mechanisms. Our review on recent findings of V(t) instability mechanisms are useful references for future development of nitride based CTF devices.