Low power adder based digital filter for QRS detector.

Area of Science:

• Electrical Engineering
• Computer Engineering

Background:

• Biomedical applications increasingly rely on dedicated processors for complex signal processing.
• Sensor networks, common in biomedical fields, face stringent low-power consumption constraints.
• Processing elements significantly impact overall system power consumption.

Purpose of the Study:

• To introduce a low-power transistor stacking technique to minimize leakage power in signal processing architectures.
• To develop and implement novel architectures for full adders and digital filters utilizing transistor stacking.
• To evaluate the effectiveness of these architectures for QRS detection in low-power sensor network applications.

Main Methods:

• Implementation of transistor stacking for reduced leakage power in full adder circuits.
• Design and integration of stacking-based architectures into a digital filter for QRS detection.
• Modeling at Register-Transfer Level (RTL) using Verilog Hardware Description Language (HDL).
• Synthesis using Synopsys Design Compiler with a 65 nm technology library.

Main Results:

• Achieved reduced leakage power at both the adder and digital filter levels.
• Demonstrated the feasibility of the low-power concept for QRS detector implementation.
• Identified a trade-off between reduced leakage power and other design quality metrics.

Conclusions:

• Transistor stacking offers a viable approach for low-power design in biomedical sensor networks.
• The proposed architectures are adaptable to various hierarchical abstraction levels based on application needs.
• The design can be optimized as a low-power corner for specific applications.